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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
June. 2000. Ver. 0.0
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTRODUCTION
S6A0075 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can display 1, 2, or 4 lines with 5 x 8 or 6 x 8 dots format.
FUNCTIONS
* * * * * * * * * * * Character type dot matrix LCD driver & controller Internal driver: 34 common and 100 segment signal output Easy interface with 4-bit or 8-bit MPU Clock synchronized serial interface 5 x 8 dot matrix / 6 x 8 dot matrix possible Bi-directional shift function All character reverse display Display shift per line Voltage converter for LCD drive voltage: 13V max. (2 times/3 times) Various instruction functions Automatic power on reset
FEATURES
* Internal memory - Character Generator ROM (CGROM): 9,600 bits (240 characters x 5 x 8 dot) - Character Generator RAM (CGRAM): 64 x 8 bits (8 characters x 5 x 8 dot) - Segment Icon RAM (SEGRAM): 16 x 8 bits (96 icons max.) - Display Data RAM (DDRAM): 80 x 8 bits (80 characters max.) Low power operation - Power supply voltage range: 2.7 - 5.5V (VDD) - LCD Drive voltage range: 3.0 - 13.0V (VDD - V5) CMOS process Programmable duty cycle: 1/17, 1/33 Internal oscillator with an external resistor Bare chip available
*
* * * *
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
PROGRAMMABLE DUTY CYCLES 5-dot Font Width Display Line Numbers 1 2 4 Duty Ratio 1/17 1/33 1/33 Single-chip Operation Displayable Characters 1 line of 40 characters 2 lines of 40 characters 4 line of 20 characters Possible Icons 80 80 80
6-dot Font Width Display Line Numbers 1 2 4 Duty Ratio 1/17 1/33 1/33 Single-chip Operation Displayable Characters 1 line of 32 characters 2 lines of 32 characters 4 line of 16 characters Possible Icons 96 96 96
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
BLOCK DIAGRAM
IE
OSC1 OSC2
Power on Reset (POR) RESET IM RS/CS E/SCLK RW/SID System Interface Serial 4-bit 8-bit 8 Instruction Register (IR)
Oscillator Timing Generator
Instruction Decoder
7 COM0Common COM33 Driver
Address Counter 7 7
Display Data RAM (DDRAM) 96 x 8-bit
34-bit Shift Register
8 8 DB4-DB7 Input/ Output Buffer Busy Flag LCD Driver Voltage Selector Data Register (DR) 8 8 COM1100-bit 100-bit Segment COM100 Shift Latch Driver Register Circuit
DB3-DB1
DB0-SOD
3
7
8
8
Vci C1 Voltage Converter C2
Segment RAM (SEGRAM) 16 bytes
Character Generator RAM (CGRAM) 64 bytes
Character Generator ROM (CGROM) 9600 bits 5
Cursor and Blink Controller
V1 - V5
V5OUT2 V5OUT3
5/6 Parallel/Serial Converter and Smooth Scroll Circuit
VDD
GND(VSS)
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
PAD CONFIGURATION
SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130
(0, 0) X
Y
Chip size: 7450 x 5340 PAD size: 100 x 100 Unit: m
S6A0075
129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24
VDD OSC2 OSC1 RESET IM IE VSS1 RS/CS RW/SID E/SCLK DB0/SOD DB1 DB2 DB3 DB4 DB5 DB6 DB7 VCI C2 C1 VSS2 V5OUT2 V5OUT3 V5 V4 V3 V2 V1
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD CENTER COORDINATES
Table 1. Pad Location
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pad Name SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 Coordinate X -2975 -2850 -2725 -2600 -2475 -2350 -2225 -2100 -1975 -1850 -1725 -1600 -1475 -1350 -1225 -1100 -975 -850 -725 -600 -475 -350 -225 -100 24 149 274 399 524 649 774 899 Y -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 Pad No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pad Name SEG100 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 VDD OSCC OSC1 RESET IM IE VSS1 RS/CS RW/SID E/SCLK DB0/SOD DB1 DB2 DB3 Coordinate X 1024 1262 1387 1512 1637 1762 1887 2012 2137 2262 2387 2512 2637 2762 2887 3012 3137 3262 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 Y -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -2504 -1750 -1625 -1500 -1375 -1250 -1125 -1000 -875 -750 -625 -500 -375 -250 -125 Pad No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pad Name DB4 DB5 DB6 DB7 VCI C2 C1 VSS2 V5OUT2 V5OUT3 V5 V4 V3 V2 V1 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 Coordinate X 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3559 3262 3137 3012 2887 2762 2637 2512 2387 2262 2137 2012 1887 1762 1637 1512 1387 1262 Y 0 125 250 375 500 625 750 875 1000 1125 1250 1375 1500 1625 1750 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504
Table 1. Pad Location (Continued)
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S6A0075
Pad No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130
Pad Name SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
Coordinate X 1024 899 774 649 524 399 274 149 24 -100 -225 -350 -475 -600 -725 -850 -975 -1100 -1225 -1350 -1475 -1600 -1725 -1850 -1975 -2100 -2225 -2350 -2475 -2600 -2725 -2850 -2975 -3559 Y 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2504 2062
Pad No. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163
Pad Name SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67
Coordinate X -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 -3559 Y 1937 1812 1687 1562 1437 1312 1187 1062 937 812 687 562 437 312 187 62 -62 -187 -312 -437 -562 -687 -812 -937 -1062 -1187 -1312 -1437 -1562 -1687 -1812 -1937 -2062
Pad No.
Pad Name
Coordinate X Y
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD DESCRIPTION
Table 2. Pad Description Pad (No) VDD (51) VSS1, VSS2 (57,72) V1 - V5 (79 - 75) Vci (69) SEG1 - SEG100 (97- 33) COM0 - COM33 (80 - 96, 34 - 50) OSC1, OSC2 (53, 52) Input Power supply Bias voltage level for LCD driving. Input voltage to the voltage converter to generate LCD drive voltage (Vci = 2.5 - 4.5V). Segment output Common output Segment signal output for LCD drive. Common signal output for LCD drive. When use internal oscillator, connect external Rf resistor. If external clock is used, connect it to OSC1. To use the voltage converter (2 times /3 times), these pins must be connected to the external capacitance. Initialized to low When IE = "High", Instruction set is selected as Table 6. When IE = "Low", Instruction set is selected as Table 10. The value of Vci is converted two times. To use three times converter, the same capacitance as that of C1-C2 should be connected here. The value of Vci is converted three times. Select Interface mode with the MPU. When IM = "Low": Serial mode, When IM = "High": 4-bit/8-bit bus mode. LCD LCD External resistor/oscillator (OSC1) External capacitance Input/ Output Name Description for logical circuit (+3V, +5V) 0V (GND) Power supply Interface
Output Output Input (OSC1), Output (OSC2) Input Input Input
Oscillator
C1, C2 (71, 70) RESET (54) IE (56)
External capacitance input Reset pin Select pin of instruction set
V5OUT2 (73) Output V5OUT3 (74)
Two times converter output Three times converter output
V5 capacitance
V5
IM (55)
Input
Interface mode selection
-
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Table 2. Pad Description (Continued) Pad (No) Input/ Output Name Description Interface
RS/CS (58)
Input
When bus mode, used as register selection input. When RS/CS = "High", data register is selected. When RS/CS = "Low", instruction Register select/ register is selected. chip select When serial mode, used as chip selection input. When RS/CS = "Low", selected. When RS/CS = "High", not elected. (low access enable) Read/Write/ When bus mode, used as read/write selection input. When RW/SID = "High", read operation. When RW/SID = "Low", write operation. When serial mode, used for data input pin. When bus mode, used as read/write enable signal. When serial mode, used as serial clock input pin. When 8-bit bus mode, used as lowest bidirectional data bit. During 4-bit bus mode, open this pin. When serial mode, used as serial data output pin. If not in read operation, open this pin. When 8-bit bus mode, used as low order bi-directional data bus. During 4-bit bus mode or serial mode, open these pins. When 8-bit bus mode, used as high order bi-directional data bus. In case of 4-bit bus mode, used as both high and low order. DB7 used for busy flag output. During serial mode, open these pins.
MPU
RW/SID (59)
Input
Serial input data
MPU
E/SCLK (60)
Input
Read/Write Enable/Serial clock
MPU
DB0/SOD (61)
Data bus 0 Input.Output/ bit/serial output Output data
MPU
DB1 - DB3 (62 - 64) Input.Output DB4 - DB7 (65 - 68)
Data bus 1-7
MPU
MPU
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
FUNCTION DESCRIPTION
SYSTEM INTERFACE This chip has all three kinds interface type with MPU: serial, 4-bit bus and 8-bit bus. Serial and bus (4-bit/8-bit) is selected by IM input, and 4-bit bus and 8-bit bus is selected by DL bit in the instruction register. During read or write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register (IR). The data register (DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM/SEGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM/SEGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/SEGRAM automatically. The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS/CS input pin in 4-bit/8-bit bus mode (IM = "High") or RS bit in serial mode (IM = "Low"). RS 0 0 1 1 R/W 0 1 0 1 Operation Instruction write operation (MPU writes Instruction code into IR) Read busy flag (DB7) and address counter (DB0 - DB6) Data write operation (MPU writes data into DR) Data read operation (MPU reads data from DR)
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S6A0075
BUSY FLAG (BF) When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7. Before executing the next instruction, be sure that BF is not high. DISPLAY DATA RAM (DDRAM) DDRAM stores display data of maximum 80 x 8 bits (80 characters). DDRAM address is set in the address counter (AC) as a hexadecimal number. (refer to Figure 1.)
MSB AC6 AC5 AC4 AC3 AC2 AC1 LSB AC0
Figure 1. DDRAM Address Display of 5-Dot Font Width Character 5-dot 1-line Display In case of 1-line display with 5-dot font, the address range of DDRAM is 00H-4FH. (refer to Figure 2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SEG100 Display Position 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 SEG1 DDRAM Address S6A0075 COM1 COM8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SEG100 COM9 COM16
COM1 COM8
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 SEG1 S6A0075
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 1F 10 11 12 13 14 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 (After Shift Left) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
COM9 COM16
COM1 COM8
4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 1F 10 11 12 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 (After Shift Right)
COM9 COM16
Figure 2. 1-line x 40ch. Display
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
5-dot 2-line Display In case of 2-line display with 5-dot font, the address range of DDRAM is 00H-27H, 40H-67H (refer to Figure 3).
1 COM1 COM8 COM17 COM24
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 SEG1 S6A0075 SEG100 Display Position COM9 COM16 COM25 COM32
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 SEG1 DDRAM Address S6A0075 1 COM1 COM8 COM17 COM24 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SEG100
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 00 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 40 (After Shift Left) COM9 COM16 COM25 COM32
1 COM1 COM8 COM17 COM24
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 (After Shift Right)
COM9 COM16 COM25 COM32
Figure 3. 2-line x 40ch. Display (5-dot Font Width)
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
5-dot 4-line Display In case of 4-line display with 5-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H -53H, 60H-73H (refer to Figure 4).
COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
Display Position DDRAM Address
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 SEG1 S6A0075 3 4 5 6 7 8 9 SEG100
1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
2
10 11 12 13 14 15 16 17 18 19 20
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 00 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 20 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 40 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 60 (After Shift Left) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
13 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 33 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 53 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 73 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 (After Shift Right)
Figure 4. 4-line x 20ch. Display (5-dot Font Width)
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
DISPLAY OF 6-DOT FONT WIDTH CHARACTER When this device is used in 6-dot font width mode, SEG97, SEG98, SEG99 and SEG100 must be open.
6-dot 1-line Display In case of 1-line display with 6-dot font, the address range of DDRAM is 00H-4FH (refer to Figure 5).
Display Position 1 COM1 COM8 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DDRAM Address S6A0075 1 COM1 COM8 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 COM9 COM16 SEG96 COM9 COM16
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F SEG1 S6A0075
SEG96 SEG1
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
(After Shift Left) 1 COM1 COM8 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 COM9 COM16
4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E (After Shift Right)
Figure 5. 1-line x 32ch. Display 6-dot 2-line Display In case of 2-line display with 6-dot font, the address range of DDRAM is 00H-27H, 40H-67H (refer to Figure 6).
Display Position 1 COM1 COM8 COM17 COM24 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F COM9 COM16 COM25 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F COM32 SEG1 SEG96 SEG96 SEG1 DDRAM Address S6A0075 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F S6A0075 1 COM1 COM8 COM17 COM24 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 COM9 COM16 COM25 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 COM32 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
(After Shift Left) 1 COM1 COM8 COM17 COM24 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 COM9 COM16 COM25 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E COM32 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E
27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E
(After Shift Right)
Figure 6. 2-line x 32ch. Display (6-dot font width)
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
6-dot 4-line Display In case of 4-line display with 6-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H, 60H-73H (refer to Figure 7).
COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Display Position DDRAM Address
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F SEG1 S6A0075 3 4 5 6 7 8 9 SEG96
1 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
2
10 11 12 13 14 15 16
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 (After Shift Left) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32
13 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 33 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 53 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 73 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E (After Shift Right)
Figure 7. 4-line x 16ch. Display (6-dot Font Width)
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
TIMING GENERATION CIRCUIT Timing generation circuit generates clock signals for the internal operations. ADDRESS COUNTER (AC) Address Counter(AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0-DB6 CURSOR/BLINK CONTROL CIRCUIT It controls cursor/blink ON/OFF and black/white inversion at cursor position. LCD DRIVER CIRCUIT LCD Driver circuit has 34 common and 100 segment signals for LCD driving. Data from SEGRAM/CGRAM/CGROM is transferred to 100-bit segment latch serially, and then it is stored to 100-bit shift latch. When each com is selected by 34-bit common register, segment data also output through segment driver from 100-bit segment latch. In case of 1-line display mode, COM0-COM17 have 1/17 duty, and in 2-line or 4-line mode, COM0-COM33 have 1/33 duty ratio.
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S6A0075
CGROM (CHARACTER GENERATOR ROM) CGROM has 5 x 8 dots 240 Character Pattern.
CGRAM (CHARACTER GENERATOR RAM) CGRAM has up to 5 x 8 dots 8 characters. By writing font data to CGRAM, user defined character can be used (refer to Table 4). 5 x 8 dots Character Pattern Table 4. Relationship between Character Code(DDRAM) and Character Pattern(CGRAM)
Character Code (DDRAM data)
CGRAM Address
CGRAM Data
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 0 x 0 0 0 0 0 0 0 0 0 B1 B0 x 0 1 1 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 1 . . . 0 1 1 1 1 1 1 1 . . . . . . 1 0 0 0 0 0 1 1 . . . 1 0 1 1 0 0 0 1 . . . 1 1 0 1 0 0 0 1 1 . . 0 0 0 0 x 1 1 1 1 . . 1 1 0 0 0 0 1 1 1 1 1 . . 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 B1 B0 x 1 1 1 1 1 1 1 0 1 0 . . 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0
Pattern Number Pattern 1
. . Pattern 8
. . . . .
. . . . .
. . . . .
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
6 x 8 Dots Character Pattern
Character Code (DDRAM data) CGRAM Address CGRAM Data D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 0 x 0 0 0 0 0 0 0 0 0 B1 B0 0 0 1 1 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 . . . 0 0 1 1 1 1 1 1 1 . . . . . . 0 1 0 0 1 0 0 0 1 . . . 0 1 0 1 1 0 0 0 1 . . . 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 . . 0 0 0 0 x 1 1 1 1 . . 1 1 0 0 0 0 1 1 1 1 . . 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 B1 B0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 . . 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0
Pattern Number Pattern 1
. . Pattern 8
. . . . .
. . . . .
. . . . .
1.
2
When BE (Blink Enable bit) = "High", blink is controlled by B1 and B0 bit. In case of 5-dot font width, when B1 = "1", enabled dots of P0-P4 will blink, and when B1 = "0" and B0 = "1", enabled dots in P4 will blink, when B1 = "0" and B0 = "0", blink will not happen. In case of 6-dot font width, when B1 = "1", enabled dots of P0-P5 will blink, and when B1 = "0" and B0 = "1", enabled dots of P5 will blink, when B1 = "0" and B0 = "0", blink will not happen. "X": Don't care
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
SEGRAM (SEGMENT ICON RAM) SEGRAM has segment control data and segment pattern data. During 1-line display mode, COM0 (COM17) makes the data of SEGRAM enable to display icons. When used in 2/4-line display mode COM0 (COM33) does that. Its higher 2-bit are blinking control data, and lower 6-bits are pattern data (refer to Table 5 and Figure 8). Table 5. Relationship between SEGRAM Address and Display Pattern
SEGRAM Address A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1. A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D7 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 D6 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 SEGRAM Data Display Pattern 5-dot Font Width D5 X X X X X X X X X X X X X X X X D4 S1 S6 S11 S16 S21 S26 S31 S36 S41 S46 S51 S56 S61 S66 S71 S76 D3 S2 S7 S12 S17 S22 S27 S32 S37 S42 S47 S52 S57 S62 S67 S72 S77 D2 S3 S8 S13 S18 S23 S28 S33 S38 S43 S48 S53 S58 S63 S68 S73 S78 D1 S4 S9 D0 S5 S10 D7 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 D6 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 B0 6-dot Font Width D5 S1 S7 S13 S19 S25 S31 S37 S43 S49 S55 S61 S67 S73 S79 S85 S91 D4 S2 S8 S14 S20 S26 S32 S38 S44 S50 S56 S62 S68 S74 S80 S86 S92 D3 S3 S9 S15 S21 S27 S33 S39 S45 S51 S57 S63 S69 S75 S81 S87 S93 D2 S4 S10 S16 S22 S28 S34 S40 S46 S52 S58 S64 S70 S76 S82 S88 S94 D1 S5 S11 S17 S23 S29 S35 S41 S47 S53 S59 S65 S71 S77 S83 S89 S95 D0 S6 S12 S18 S24 S30 S36 S42 S48 S54 S60 S66 S72 S78 S84 S90 S96
S14 S15 S19 S20 S24 S25 S29 S30 S34 S35 S39 S40 S44 S45 S49 S50 S54 S55 S59 S60 S64 S65 S69 S70 S74 S75 S79 S80
B1, B0: Blinking control bit
Control Bit BE B1 B0 0XX 100 101 11X
1. 2.
Blinking Port 5-dot font width No blink No blink D4 D4 - D0 6-dot font width No blink No blink D5 D5 - D0
S1-S80 : Icon pattern ON/OFF in 5-dot font width S1-S96 : Icon pattern ON/OFF in 6-dot font width "X": Don't care.
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
5-Dot Font Width (FW = 0)
S1
S2
S3
S4
S5
S6
S7
S8
S9 S10
S76 S77 S78 S79 S80
S81 S82 S83 S84 S85
S96 S97 S98 S99 S100
SEG10
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG96
SEG97
SEG98
SEG99 SEG95
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
...
...
6-Dot Font Width (FW = 1)
S1
S2
S3
S4
S5
S6
S7
S8
S9 S10 S11 S12
S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96
SEG10
SEG11
SEG12
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
...
...
Figure 8. Relationship between SEGRAM and Segment Display
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SEG96
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG100
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
INSTRUCTION DESCRIPTION
OUTLINE To overcome the speed difference between internal clock of S6A0075 and MPU clock, S6A0075 performs internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus. (refer to Table 6/10) Instruction can be divided largely four kinds, * * * * S6A0075 function set instructions (set display methods, set data length, etc.) Address set instructions to internal RAM Data transfer instructions with internal RAM Others .
The address of internal RAM is automatically increased or decreased by 1. When IE = "High", S6A0075 is operated according to instruction set 1 (Table 6) and when IE = "Low", S6A0075 is operated according to instruction set 2 (Table 10).
NOTE: During internal operation, busy flag (DB7) is read high. Busy flag check must precede the next instruction. When an MPU program with Busy Flag (DB7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by the falling edge of the "E" signal after the Busy Flag (DB7) goes to "Low".
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
INSTRUCTION DESCRIPTION 1 (IE = "HIGH") Table 6. Instruction Set 1
Instruction Code Instruction RE RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Executi on Time (fosc = 270kHz) 1.53ms
Clear display
X
0
0
0
0
0
0
0
0
0
1
Write "20H" to DDRAM. and set DDRAM address to "00H" from AC.
Return home
0
0
0
0
0
0
0
0
0
1
x
Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The 1.53ms contents of DDRAM are not changed. Set power down mode bit. PD = "1":power down mode set, PD = "0":power down mode disable Assign cursor moving direction. I/D = "1": increment, I/D = "0": decrement and display shift enable bit. S = "1": make display shift of the enabled lines by the DS4 DS1 bits in the shift enable instruction. S = "0": display shift disable Segment bi-direction function. BID = "0": Seg1 Seg80, BID = "1": Seg80 Seg1. Set display/cursor/blink on/off D = "1": display on, D = "0": display off, C = "1": cursor on, C = "0": cursor off, B = "1": blink on, B = "0": blink off.
Power down mode
1
0
0
0
0
0
0
0
0
1
PD
39s
0 Entry mode set
0
0
0
0
0
0
0
1
I/D
S
39s
1
0
0
0
0
0
0
0
1
1
B/D
Display ON/OFF Control
0
0
0
0
0
0
0
1
D
C
B
39s
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Table 6. Instruction Set 1 (Continued)
Instruction Code Instruction RE RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Executi on Time (fosc = 270kHz)
Extended function set
1
0
0
0
0
0
0
1
FW B/W NW
Assign font width, black/white inverting of cursor, and 4-line display mode control bit. FW = "1": 6-dot font width, FW = "0": 5-dot font width, B/W = "1": black/white inverting of cursor enable, B/W = "0": black/white inverting of cursor disable NW = "1": 4-line display mode, NW = "0": 1-line or 2-line display mode. Cursor or display shift. S/C = "1": display shift, S/C = "0": cursor shift, R/L = "1": shift to right, R/L = "0": shift to left.
39s
Cursor or Display Shift
0
0
0
0
0
0
1
S/C
R/L
x
x
39s
Shift Enable
1
0
0
0
0
0
1
(when DH = "1") Determine the line for display shift. DS1 = "1/0": 1st line display shift enable/disable DS2 = "1/0": 2nd line display shift DS4 DS3 DS2 DS1 enable/disable DS3 = "1/0": 3rd line display shift enable/disable DS4 = "1/0": 4th line display shift enable/disable. (when DH = "0") Determine the line for horizontal smooth scroll. HS1 = "1/0": 1st line dot scroll enable/disable HS4 HS3 HS2 HS1 HS2 = "1/0": 2nd line dot scroll enable/disable HS3 = "1/0": 3rd line dot scroll enable/disable HS4 = "1/0": 4th line dot scroll enable/disable.
39s
Scroll enable
1
0
0
0
0
0
1
39s
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Table 6. Instruction Set 1 (Continued)
Instruction Code Instruction RE RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Executio n Time (fosc = 270kHz)
0 Function set
0
0
0
0
1
DL
N
RE (0)
DH
REV
Set interface data length (DL = "1": 8-bit, DL = "0": 4-bit), numbers of display line when NW = "0", (N = "1": 2-line, N = "0" : 1-line), extension register, RE("0"), shift/scroll enable DH = "1": display shift enable DH = "0": dot scroll enable. reverse bit REV = "1": reverse display, REV = "0": normal display. Set DL, N, RE("1") and CGRAM/SEGRAM blink enable BE) BE = " 1/0": CGRAM/SEGRAM blink enable/disable Set CGRAM address in address counter. Set SEGRAM address in address counter. Set DDRAM address in address counter. Set the quantity of horizontal dot scroll.
39s
1
0
0
0
0
1
DL
N
RE (1)
BE
0
39s
Set CGRAM address Set SEGRAM address Set DDRAM address Set scroll quantity
0
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
39s
1
0
0
0
1
X
X
AC3 AC2 AC1 AC0
39s
0
0
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0 QC 5 QC 4 QC 3 QC 2 QC 1 QC 0
39s
1
0
0
1
X
39s
Read busy flag and address
X
0
1
BF
Can be known whether during internal operation or not by reading BF. The contents of AC6 AC5 AC4 AC3 AC2 AC1 AC0 address counter can also be read. BF = "1": busy state BF = "0": ready state D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Write data into internal RAM (DDRAM / CGRAM / SEGRAM). Read data from internal RAM (DDRAM / CGRAM / SEGRAM).
0s
Write data Read data
X X
1 1
0 1
D7 D7
43s 43s
NOTES: 1. When an MPU program with busy flag (DB7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by the "E" signal after the busy flag (DB7) goes to "Low" 2. "X": Don't care
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Display Clear RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). Return Home: (RE = 0) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change. Power Down Mode Set: (RE = 1) RS 1 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 PD
Power down mode enable bit set instruction. When PD = "High", it makes S6A0075 suppress current consumption except the current needed for data storage by executing next three functions. * * * Make the output value of all the COM/SEG ports VDD Make the COM/SEG output value of extension driver VDD by setting D output to "High" and M output to "Low" Disable voltage converter to remove the current through the divide resistor of power supply. You can use this instruction as power sleep mode. When PD = "Low", power down mode becomes disabled.
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Entry Mode Set (RE = 0) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 S
Set the moving direction of cursor and display. I/D: Increment/decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
- CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM. When S = "High", after DDRAM write, the display of enabled line by DS1 - DS4 bits in the shift enable instruction is shifted to the right (I/D = "0") or to the left (I/D = "1"). But it will seem as if the cursor does not move. When S = "Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of display like this function is not performed. (RE = 1) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 1 DB0 BID
Set the data shift direction of segment in the application set. BID: Data shift direction of segment When BID = "Low", segment data shift direction is set to normal order from SEG1 to SEG100. When BID = "High", segment data shift direction is set to reverse from SEG100 to SEG1. By using this instruction, you can raise the efficiency of application board area.
- The BID setting instruction is recommended to be set at the same time level of function set instruction. - DB1 bit must be set to "1".
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Display ON / OFF Control (RE = 0) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
Control display/cursor/blink ON/OFF 1 bit register. D: Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. If fosc has 270kHz frequency, blinking has 370 ms interval. When B = "Low", blink is off.
C:
B:
Extended Function Set (RE = 1) RS 0 FW: R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 FW DB1 B/W DB0 NW
Font Width control When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5 times than that of 5-dot font width. The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost space bit of CGRAM.(refer to Figure 9) When FW = "Low", 5-dot font width is set. Black/White Inversion enable bit When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270kHz, inversion has 370 ms intervals. 4 Line mode enable bit When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't care condition.
B/W:
NW:
6-bit S p a c e CGROM Characte Font (5-dot) CGROM
6-bit CGRAM Characte Font (6-dot) CGRAM
8-bit
8-bit
Figure 9. 6-dot Font Width CGROM/CGRAM
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Cursor or Display Shift (RE = 0) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 S/C DB2 R/L DB1 X DB0 X
Shift right/left cursor position or display, without writing or reading of display data, this instruction is use to correct or search display data (refer to Table 7). During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. When 4-line mode, cursor moves to the next line, only after every 20th digit of the current line. Note that display shift is performed simultaneously in all the line enabled by DS1-DS4 in the shift enable instruction. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed. During low power consumption mode, display shift may not be performed normally. Table 7. Shift Patterns According to S/C and R/L Bits S/C 0 0 1 1 R/L 0 1 0 1 Operation Shift cursor to the left, address counter is decreased by 1 Shift cursor to the right, address counter is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Shift/Scroll Enable (RE = 1) (DH = 0) RS 0 HS: R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 HS4 DB2 HS3 DB1 HS2 DB0 HS1
Horizontal scroll per line enable This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and each scroll is performed individually in each line. If you want to scroll the line in 1-line display mode or the 1st line in 2-line display mode, set HS1 and HS2 to "High". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High". (refer to Table 8)
(DH = 1) RS 0 DS: R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 DS4 DB2 DS3 DB1 DS2 DB0 DS1
Display shift per line enable this instruction selects shifting line to be shifted according to each line mode in display shift right/left instruction. DS1, DS2, DS3 and DS4 indicate each line to be shifted, and each shift is performed individually in each line. If you set DS1 and DS2 to "High" (enable) in 2 line mode, only the 1st line is shifted and the 2nd line is not shifted. When only DS1 = "High", only the half of the 1st line is shifted. If all the DS bits (DS1 to DS4) are set to "Low" (disable), no display is shifted.
Table 8. Relationship between DS and COM signal Enable Bit HS1/DS1 HS2/DS2 HS3/DS3 HS4/DS4 Enabled Common Signals During Shift COM1 - COM8 COM9 - COM16 COM17 - COM24 COM25 - COM32 The part of display line that corresponds to enabled common signal can be shifted. Description
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Function Set (RE = 0) RS 0 DL: R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 RE(0) DB1 DH DB0 REV
Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it needs to transfer 4-bit data by two times. Display line number control bit It is variable only when NW bit of extended function set instruction is low. When N = "Low", it means 1-line display mode. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, it means 4-line mode independent of N bit. Extended function registers enable bit At this instruction, RE must be "Low". Display shift enable selection bit. When DH = "High", display shift per line becomes enable. When DH = "Low", smooth dot scroll becomes enable. This bit can be accessed only when IE pin input is "High". Reverse enable bit When REV = "High", all the display data are reversed. Namely, all the white dots become black and black dots become white. When REV = "Low", the display mode set normal display.
N:
RE: DH:
REV:
(RE = 1) RS 0 DL: R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 RE(1) DB1 BE DB0 0
Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it needs to transfer 4-bit data by two times. Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", it means 1-line display mode. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, it means 4-line mode independent of N bit. Extended function registers enable bit When RE = "High", extended function set registers, SEGRAM address set registers, BID bit, HS/DS bits of shift/scroll enable instruction and BE bits of function set register can be accessed. CGRAM/SEGRAM data blink enable bit If BE is "High", It makes user font of CGRAM and segment of SEGRAM blink. The quantity of blink is assigned the highest 2 bit of CGRAM/SEGRAM.
N:
RE:
BE:
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Set CGRAM Address (RE = 0) RS 0 R/W 0 DB7 0 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. Set SEGRAM Address (RE = 1) RS 0 R/W 0 DB7 0 DB6 1 DB5 X DB4 X DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. Set DDRAM Address (RE = 0) RS 0 R/W 0 DB7 1 DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" - "27H", and DDRAM address in the 2nd line is from "40H" - "67H". In 4-line display mode (NW = 1), DDRAM address is from "00H" - "13H" in the 1st line, from "20H" to "33H" in the 2nd line, from "40H" - "53H" in the 3rd line and from "60H" - "73H" in the 4th line. Set Scroll Quantity (RE = 1) RS 0 R/W 0 DB7 1 DB6 X DB5 SQ DB4 SQ4 DB3 SQ3 DB2 SQ2 DB1 SQ1 DB0 SQ0
As set SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units (Refer to Table 9). In this case S6A0075 can show hidden areas of DDRAM by executing smooth scroll from 1 to 48 dots. Table 9. Scroll Quantity According to HDS bits SQ5 0 0 0 0 : 1 1 SQ4 0 0 0 0 : 0 1 SQ3 0 0 0 0 : 1 X SQ2 0 0 0 0 : 1 X SQ1 0 0 1 1 : 1 X SQ0 0 1 0 1 : 1 X No shift Shift left by 1-dot Shift left by 2-dot Shift left by 3-dot : Shift left by 47-dot Shift left by 48-dot Function
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S6A0075
100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
Read Busy Flag & Address RS 0 R/W 1 DB7 BF DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
This instruction shows whether S6A0075 is in internal operation or not. If the resultant BF is High, it means the internal operation is in progress and you have to wait until BF to be Low, and then the next instruction can be performed. In this instruction you can read also the value of address counter. Write Data to RAM RS 1 R/W 0 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction: DDRAM address set, CGRAM address set, SEGRAM address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. Read Data From RAM RS 1 R/W 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly. In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction.
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
INSTRUCTION DESCRIPTION 2 (IE = "LOW") Table 10. Instruction Set 2
Instruction Code Instruction RE RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Executi on Time (fosc = 270kHz) 1.53ms
Clear display
X
0
0
0
0
0
0
0
0
0
1
Write "20H" to DDRAM. and set DDRAM address to "00H" from AC. Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Assign cursor moving direction. I/D = "1": increment, I/D = "0": decrement. and display shift enable bit. S = "1": make entire display shift of all lines during DDRAM write, S = "0": display shift disable Set display/cursor/blink on/off D = "1": display on, D = "0": display off, C = "1": cursor on, C = "0": cursor off, B = "1": blink on, B = "0": blink off. Assign font width, black/white inverting of cursor, and 4-line display mode control bit. FW = "1": 6-dot font width, FW = "0": 5-dot font width, B/W = "1": black/white inverting of cursor enable, B/W = "0": black/white inverting of cursor disable NW = "1": 4-line display mode, NW = "0": 1-line or 2-line display mode Cursor or display shift. S/C = "1": display shift, S/C = "0": cursor shift, R/L = "1": shift to right, R/L = "0": shift to left
Return home
X
0
0
0
0
0
0
0
0
1
x
1.53ms
Entry mode set
X
0
0
0
0
0
0
0
1
I/D
S
39s
Display ON/OFF control
0
0
0
0
0
0
0
1
D
C
B
39s
Extended function set
1
0
0
0
0
0
0
1
FW B/W NW
39s
Cursor or display shift
0
0
0
0
0
0
1
S/L
R/L
X
X
39s
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Table 10. Instruction Set 2 (Continued)
Instruction Code Instruction RE RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Executi on Time (fosc = 270kHz)
Scroll Enable
1
0
0
0
0
0
1
Determine the line for horizontal smooth scroll. HS1 = "1/0": 1st line dot scroll enable/disable HS2 = "1/0": 2nd line dot scroll HS4 HS3 HS2 HS1 enable/disable HS3 = "1/0": 3rd line dot scroll enable/disable HS4 = "1/0": 4th line dot scroll enable/disable Set interface data length DL = "1": 8-bit, DL = "0": 4-bit numbers of display line when NW = "0", N = "1": 2-line, N = "0": 1-line extension register, RE("0") Set DL, N, RE("1") and CGRAM/SEGRAM blink enable (BE) BE = " 1/0": CGRAM/SEGRAM blink enable/disable Set CGRAM address in address counter. Set SEGRAM address in address counter. Set DDRAM address in address counter. Set the quantity of horizontal dot scroll.
39s
0 Function Set
0
0
0
0
1
DL
N
RE (0)
X
X
39s
1
0
0
0
0
1
DL
N
RE (1)
BE
0
39s
Set CGRAM address Set SEGRAM address Set DDRAM address Set scroll quantity
0
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
39s
1
0
0
0
1
X
X
AC3 AC2 AC1 AC0
39s
0
0
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0
39s
1
0
0
1
X
SQ5
SQ4
SQ3
SQ2 SQ1
SQ0
39s
Read busy flag and address
X
0
1
BF
Can be known whether during internal operation or not by reading BF. The contents of AC6 AC5 AC4 AC3 AC2 AC1 AC0 address counter can also be read. BF = "1": busy state, BF = "0": ready state.
0s
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S6A0075
Table 10. Instruction Set 2 (Continued)
Instruction Code Instruction RE RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Execution Time (fosc = 270kHz) 43s 43s
Write data Read data
X X
1 1
0 1
D7 D7
D6 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 D0
Write data into internal RAM (DDRAM / CGRAM / SEGRAM). Read data from internal RAM (DDRAM / CGRAM / SEGRAM).
Note: 1. When an MPU program with Busy Flag (DB7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by the falling edge of the "E" signal after the Busy Flag (DB7) goes to "Low". 2. "X": Don't care.
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Display Clear RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. And entry mode is set to increment mode (I/D = "1"). Return Home RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change. Entry Mode Set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 S
Set the moving direction of cursor and display. I/D: Increment/decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
- CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM. When S = "High", after DDRAM write, the entire display of all lines is shifted to the right (I/D = "0") or to the left (I/D = "1"). But it will seem as if the cursor does not move. When S = "Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of entire display is not performed.
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S6A0075
Display ON/OFF Control (RE = 0) RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
Control display/cursor/blink ON/OFF 1 bit register. D: Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. If fosc has 270kHz frequency, blinking has 370 ms interval. When B = "Low", blink is off.
C:
B:
Extended Function Set (RE = 1) RS 0 FW: R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 FW DB1 B/W DB0 NW
Font width control When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5 times than that of 5-dot font width. The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost pace bit of CGRAM.(Refer to Fig-10) When FW = "Low", 5-dot font width is set. Black/White Inversion enable bit When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270kHz, inversion has 370 ms intervals. 4 Line mode enable bit When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't care condition.
B/W:
NW:
6-bit S p a c e CGROM Characte Font (5-dot) CGROM
6-bit CGRAM Characte Font (6-dot) CGRAM
8-bit
8-bit
Figure 10. 6-dot font width CGROM/CGRAM
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Cursor or Display Shift (RE = 0) RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 1 S/C R/L X X Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to correct or search display data.(Refer to Table 11) during 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. When 4-line mode, cursor moves to the next line, only after every 20th digit of the current line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed. Table 11. Shift Patterns According to S/C and R/L Bits S/C 0 0 1 1 R/L 0 1 0 1 Operation Shift cursor to the left, address counter is decreased by 1 Shift cursor to the right, address counter is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
Scroll Enable (RE = 1) RS 0 HS: R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 HS4 DB2 HS3 DB1 HS2 DB0 HS1
Horizontal scroll per line enable This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and each scroll is performed individually in each line. If you want to scroll the line in 1-line display mode or the 1st line in 2-line display mode, set HS1 and HS2 to "High". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High". (refer to Table 8)
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S6A0075
Function Set (RE = 0) RS 0 DL: R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 1 DL N RE(0) X X Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it needs to transfer 4-bit data by two times. Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", it means 1-line display mode. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, it means 4-line mode independent of N bit. Extended function registers enable bit At this instruction, RE must be "Low".
N:
RE:
(RE = 1) RS 0 DL: R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 1 DL N RE(1) BE 0 Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When 4-bit bus mode, it needs to transfer 4-bit data by two times. Display line number control bit It is variable only when NW bit of extended function set instruction is Low. When N = "Low", it means 1-line display mode. When N = "High", 2-line display mode is set. When NW = "High", N bit is invalid, it means 4-line mode independent of N bit. Extended function registers enable bit When RE = "High", extended function set registers, SEGRAM address set registers, HS bits of scroll enable instruction and BE bits of function set register can be accessed. CGRAM/SEGRAM data blink enable bit If BE is "High", It makes user font of CGRAM and segment of SEGRAM blink. The quantity of blink is assigned the highest 2 bit of CGRAM/SEGRAM.
N:
RE:
BE:
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Set CGRAM Address (RE = 0) RS 0 R/W 0 DB7 0 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. Set SEGRAM Address (RE = 1) RS 0 R/W 0 DB7 0 DB6 1 DB5 X DB4 X DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set SEGRAM address to AC. This instruction makes SEGRAM data available from MPU. Set DDRAM Address (RE = 0) RS 0 R/W 0 DB7 1 DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". In 4-line display mode (NW = 1), DDRAM address is from "00H" to "13H" in the 1st line, from "20H" to "33H" in the 2nd line, from "40H" to "53H" in the 3rd line and from "60H" to "73H" in the 4th line.
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S6A0075
Set Scroll Quantity (RE = 1) RS 0 R/W 0 DB7 1 DB6 X DB5 SQ5 DB4 SQ4 DB3 SQ3 DB2 SQ2 DB1 SQ1 DB0 SQ0
As set SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units (refer to Table 12). In this case S6A0075 execute dot smooth scroll from 1 to 48 dots. Table 12. Scroll Quantity According to HDS bits SQ5 0 0 0 0 : 1 1 SQ4 0 0 0 0 : 0 1 SQ3 0 0 0 0 : 1 X SQ2 0 0 0 0 : 1 X SQ1 0 0 1 1 : 1 X SQ0 0 1 0 1 : 1 X No shift Shift left by 1-dot Shift left by 2-dot Shift left by 3-dot : Shift left by 47-dot Shift left by 48-dot Function
Read Busy Flag & Address RS 0 R/W 1 DB7 BF DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
This instruction shows whether S6A0075 is in internal operation or not. If the resultant BF is High, it means the internal operation is in progress and you have to wait until BF to be low, and then the next instruction can be performed. In this instruction you can read also the value of address counter. Write Data to RAM RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set, SEGRAM address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode.
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Read Data From RAM RS 1 R/W 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly. - In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction.
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S6A0075
INTERFACE WITH MPU
S6A0075 can transfer data in bus mode (4-bit or 8-bit) or serial mode with MPU. So you can use any type 4 or 8bit MPU. In case of 4-bit bus mode, data transfer is performed by two times to transfer 1 byte data. * * When interfacing data length are 4-bit, only 4 ports, from DB4 - DB7, are used as data bus. At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then lower 4bit (in case of 8-bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed by two times. Busy flag outputs "High" after the second transfer are ended. When interfacing data length are 8-bit, transfer is performed at a time through 8 ports, from DB0 - DB7. If IM is set to "Low", serial transfer mode is set.
* *
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INTERFACE WITH MPU IN BUS MODE Interface with 8-bit MPU If 8-bit MPU is used, S6A0075 can connect directly with that. In this case, port E, RS, R/W and DB0 - DB7 need to interface each other. Example of timing sequence is shown below.
RS R/W E Internal Signal DB7
Data Internal Operation No Bus y
Busy
Busy
Data
Instruction
Busy Flag Check
Busy Flag Check
Busy Flag Check
Instruction
Figure 11. Example of 8-bit Bus Mode Timing Sequence Interface with 4-bit MPU If 4-bit MPU is used, S6A0075 can connect directly with this. In this case, port E, RS, R/W and DB4 - DB7 need to interface each other. The transfer is performed by two times. Example of timing sequence is shown below.
RS R/W E Internal Signal DB7
D7 D3 Internal Operation No Busy
Busy
AC3
AC3
D7
D3
Instruction
Busy Flag Check
Busy Flag Check
Instruction
Figure 12. Example of 4-bit Bus Mode Timing Sequence
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S6A0075
INTERFACE WITH MPU IN SERIAL MODE When IM port input is "Low", serial interface mode is started. At this time, all three ports, SCLK (synchronizing transfer clock), SID (serial input data), and SOD (serial output data), are used. If you want to use S6A0075 with other chips, chip select port (CS) can be used. By setting CS to "Low", S6A0075 can receive SCLK input. If CS is set to "High", S6A0075 reset the internal transfer counter. Before transfer real data, start byte has to be transferred. It is composed of succeeding 5 "High" bits, read write control bit (R/W), register selection bit (RS) and end bit that indicates the end of start byte. Whenever succeeding 5 "High" bits are detected by S6A0075, it makes serial transfer counter reset and ready to receive next information. The next input data are register selection bit that determine which register will be used, and read write control bit that determine the direction of data. Then end bit is transferred, which must have "Low" value to show the end of start byte. (Refer to Figure 13. Figure 14) Write Operation (R/W = 0) After start byte is transferred from MPU to S6A0075, 8-bit data is transferred which is divided into 2 bytes, each byte has 4 bit's real data and 4 bit's partition token data. For example, if real data is "10110001" (D0 - D7), then serially transferred data becomes "1011 0000 0001 0000" where 2nd and 4th 4 bits must be "0000" for safe transfer. To transfer several bytes continuously without changing RS bit and RW bit, start byte transfer is needed only at first starting time. Namely, after first start byte is transferred, real data can be transferred succeeding. Read Operation (R/W = 1) After start byte is transferred to S6A0075, MPU can receive 8-bit data through the SOD port at a time from the LSB. Wait time is needed to insert between start byte and data reading, because internal reading from RAM requires some delay. Continuous data reading is possible like serial write operation. It also needs only one start bytes, only if you insert some delay between reading operations of each byte. During the reading operation, S6A0075 observes succeeding 5 "High" from MPU. If it is detected, S6A0075 restarts serial operation at once and ready to receive RS bit. So in continuous reading operation, SID port must be "Low".
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Serial Write Operation CS (Input)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK (Input) SID (Input)
"1" "1" "1" "1" "1" R/W RS 0 D0 D1 D2 D3 "0" "0" "0" "0" D4 D5 D6 D7 "0" "0" "0" "0"
Starting Byte Synchronizing Bit String Lower Data 1'st Byte
Instruction Upper Data
2'nd Byte
Serial Read Operation CS (Input)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCLK (Input) SID (Input)
"1" "1" "1" "1" "1" R/W RS "0" "0" "0" "0" "0" "0" "0" "0" "0"
SOD (Output) Starting Byte
D0 D1 D2 D3 D4 D5 D6 D7
Busy Flag/ Read Data Lower Data Upper Data
Synchronizing Bit String
Figure 13. Timing Diagram of Serial Data Transfer
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S6A0075
Continuous Write Operation SCLK SID
Start Byte 1'st Byte 2'nd Byte
Wait
1'st Byte 2'nd Byte
Wait
1'st Byte 2'nd Byte
Instruction1
Instruction2 Instruction1 Execution Time
Instruction3 Instruction2 Execution Time
Instruction3 Execution Time
Continuous Read Operation SCLK SID SOD
Start Byte Data Read1 Data Read2 Data Read3
Wait
Wait
Wait
Instruction1 Execution Time
Instruction2 Execution Time
Instruction3 Execution Time
Figure 14. Timing Diagram of Continuous Data Transfer
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APPLICATION INFORMATION ACCORDING TO LCD PANEL
LCD Panel: 40 Character x 1-line Format (5-dot Font,1/17 Duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG98 SEG99 SEG100 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9

S6A0075
LCD Panel: 40 Character x 2-line Format (5-dot Font, 1/33 Duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM33 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG98 SEG99 SEG100 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
S6A0075
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LCD Panel: 20 Character x 4-line Format (5-dot Font, 1/33 Duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG98 SEG99 SEG100
S6A0075
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LCD Panel: 16 Character x 4-line Format (6-dot Font, 1/33 Duty)
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 (COM0) SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100
S6A0075

Open Open Open Open
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S6A0075
INITIALIZING
INITIALIZING BY INTERNAL RESET CIRCUIT When the power is turned on, S6A0075 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF(Busy Flag) is kept "High"(busy state) to the end of initialization. Display Clear instruction Write "20H" to all DDRAM Set Functions instruction DL = 1: 8-bit bus mode N = 1: 2-line display mode RE = 0: Extension register disable BE = 0: CGRAM/SEGRAM blink OFF DH = 0: Horizontal scroll enable REV = 0: Normal display (Not reversed display) Control Display ON/OFF instruction D = 0: Display OFF C = 0: Cursor OFF B = 0: Blink OFF Set Entry Mode instruction I/D = 1: Increment by 1 S = 0: No entire display shift BID = 0: Normal direction segment port Set Extension Function instruction FW = 0: 5-dot font width character display B/W = 0: Normal cursor (8th line) NW = 0: Not 4-line display mode, 2-line mode is set because of N("1") Enable Shift instruction HS = 0000: Scroll per line disable DS = 0000: Shift per line disable Set scroll Quantity instruction SQ = 000000: Not scroll INITIALIZING BY HARDWARE RESET INPUT When RESET pin = "Low", S6A0075 can be initialized like the case of power on reset. During the power on reset operation, this pin is ignored.
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INITIALIZING BY INSTRUCTION
8-BIT INTERFACE MODE
Power On
Wait for more than 20ms after VDD rises to 4.5V Wait for more than 30ms after VDD rises to 2.7V (DL = "1") Function Set RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL(1) DB3 N DB2 0 DB1 x DB0
Condition: fosc = 270kHz
0 DL 1 0
4-bit interface 8-bit interface 1-line mode 2-line mode
x
N 1
Wait for more than 39s 0 D Display ON/OFF Control RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 C B B Wait for more than 39s 1 Blink on 1 0 Cursor on Blink off 1 0 Display on Cursor off Display off
Clear Display RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Wait for more than 1.53sms 0 Entry Mode Set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 0 S S 1 Initialization End Entire shift on Entire shift off I/D 1 Increment mode Decrement mode
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S6A0075
4-BIT INTERFACE MODE
Power On
Wait for more than 20ms after VDD rises to 4.5V Wait for more than 30ms after VDD rises to 2.7V (DL = "0") Function Set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Condition: fosc = 270kHz 0 DL 1 0 8-bit interface 1-line mode 2-line mode 4-bit interface
0
0
0
1
DL(0)
x
x
x
x
N 1
Wait for more than 39s
Function Set RS 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 N 0 x 1 x 0 x x x x x x x x x
Wait for more than 39s 0 D Display ON/OFF Control RS 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 C 0 0 0 1 0 D 0 C 0 B x x x x x x x x B 1 Wait for more than 39s Blink on 1 0 Cursor on Blink off 1 0 Display on Cursor off Display off
Display Clear RS 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 x x x x x x x x
Wait for more than 1.53ms
Entry Mode Set I/D RS 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 I/D 0 SH x x x x x x x S x
0 1 0 1
Decrement mode Increment mode Entire shift off Entire shift on
Initialization End
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EXAMPLE OF INSTRUCTION AND DISPLAY CORRESPONDENCE
IE = "LOW"
1. Power supply on: Initialized by the internal power on reset circuit RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LCD DISPLAY
2. Function Set: 8-bit, 1-line, RE(0) RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 1 0 X X
3. Display ON/OFF Control: Display/Cursor on RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 _ 0 0 0 0 0 1 1 1 0
4. Entry Mode Set: Increment RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 _ 0 0 0 0 0 0 1 1 0
5. Write Data to DDRAM: Write S RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S_ 0 0 1 0 1 0 0 1 1
6. Write Data to DDRAM: Write A RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SA_ 0 0 1 0 0 0 0 0 1
7. Write Data to DDRAM: Write M RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SAM_ 0 0 1 0 0 1 1 0 1
8. Write Data to DDRAM: Write S RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SAMS_ 0 0 1 0 1 0 0 1 1
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
9. Write Data to DDRAM: Write U RS 1 R/W 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 0 1 0 1
LCD DISPLAY SAMSU_
10. Write Data to DDRAM: Write N RS 1 R/W 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 1 1 1 0 SAMSUN_
11. Write Data to DDRAM: Write G RS 1 R/W 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 0 1 1 1 SAMSUNG_
12. Cursor or Display Shift: Cursor shift to right RS 0 R/W 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SAMSUNG _ 0 0 0 1 0 1 X X
13. Entry Mode Set: Entire Display Shift Enable RS 0 R/W 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SAMSUNG _ 0 0 0 0 0 1 1 1
14. Write Data to DDRAM: Write K RS 1 R/W 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AMSUNG K_ 0 1 0 0 1 0 1 1
15. Write Data to DDRAM: Write S RS 1 R/W 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSUNG KS_ 0 1 0 1 0 0 1 1
16. Write Data to DDRAM: Write 0 RS 1 R/W 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SUNG KS0_ 0 0 1 1 0 0 0 0
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
17. Write Data to DDRAM: Write 0 RS 1 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 0 DB1 0 DB0 0
LCD DISPLAY UNG KS00_
18. Write Data to DDRAM: Write 7 RS 1 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 1 DB1 1 DB0 1 NG KS007_
19. Write Data to DDRAM: Write 3 RS 1 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 0 DB1 1 DB0 1 G KS0073_
20. Cursor or Display Shift: Cursor shift left RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 1 DB3 0 DB2 0 DB1 x DB0 x G KS0073
21. Write Data to DDRAM: Write 8 RS 1 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 1 DB1 0 DB0 1 KS0075_
22. Return Home RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 x SAMSUNG KS0075
23. Clear Display RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1 _
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S6A0075
IE = "HIGH"
1. Power Supply On: Initialized by the internal power on reset circuit RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
2. Function Set: 8-bit, RE(1) RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 1 DB1 0 DB0 0
3. Extended Function Set: 5-font, 4-line RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 0 DB1 0 DB0 1
4. Function Set: RE(0) RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0
5. Display ON/OFF Control: Display/Cursor on RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 1 DB1 1 DB0 0
_
6. Write Data to DDRAM: Write S RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 1 DB0 1
S_
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
7. Write Data to DDRAM: Write A RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
SA_
12. Write Data to DDRAM: Write G RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 1 DB1 1 DB0 1
SAMSUNG_
13. Set DDRAM Address 20H RS 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
SAMSUNG _
14. Write Data to DDRAM: Write K RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 0 DB1 1 DB0 1
SAMSUNG K_
19. Write Data to DDRAM: Write 5 RS 1 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 0 DB2 1 DB1 0 DB0 1
SAMSUNG KS0075_
20. Set DDRAM Address 40H RS 0 R/W 0 DB7 1 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
SAMSUNG KS0075 _
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
21. Write Data to DDRAM: Write L RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 1 DB1 0 DB0 0
SAMSUNG KS0075 L_
30. Write Data to DDRAM: Write R RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 1 DB0 0
SAMSUNG KS0075 LCD DRIVER_
31. Set DDRAM Address 60H RS 0 R/W 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
SAMSUNG KS0075 LCD DRIVER _
43. Write Data to DDRAM: Write R RS 1 R/W 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 0 DB1 1 DB0 0
SAMSUNG KS0075 LCD DRIVER & CONTROLLER_
44. Function Set: RE("0"), DH("1") RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 1 DB0 0
SAMSUNG KS0075 LCD DRIVER & CONTROLLER_
45. Function Set: RE("1") RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 1 DB1 0 DB0 0
SAMSUNG KS0075 LCD DRIVER & CONTROLLER_
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
46. Shift/Scroll Enable: DS4("1"), DS3/2/1("0") RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0
SAMSUNG KS0075 LCD DRIVER & CONTROLLER_
47. Function Set: RE("0") RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 1 DB0 0
SAMSUNG KS0075 LCD DRIVER & CONTROLLER_
48. Cursor or Display Shift: Display shift to left RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 0 DB1 x DB0 x
SAMSUNG KS0075 LCD DRIVER CONTROLLER_
49. Cursor or Display Shift: Display shift to left RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 0 DB1 x DB0 x
SAMSUNG KS0075 LCD DRIVER CONTROLLER_
50. Cursor or Display Shift: Display shift to left RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 0 DB1 x DB0 x
SAMSUNG KS0075 LCD DRIVER ONTROLLER_
51. Cursor or Display Shift: Display shift to left RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 0 DB1 x DB0 x
SAMSUNG KS0075 LCD DRIVER NTROLLER_
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S6A0075
52. Return Home RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 x
SAMSUNG KS0075 LCD DRIVER & CONTROLLER
53. Function Set: RE("0), REV("1") RS 0 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 1 DB0 1
SAMSUNG KS0075 LCD DRIVER & CONTROLLER
54. Cursor or Display Shift: Display shift to right RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 1 DB1 x DB0 x
SAMSUNG KS0075 LCD DRIVER & CONTROLLER
55. Cursor or Display Shift: Display shift to right RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 1 DB1 x DB0 x
SAMSUNG KS0075 LCD DRIVER & CONTROLLER
56. Return Home RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 x
SAMSUNG KS0075 LCD DRIVER & CONTROLLER
57. Function Set: RE("0"), REV("0") RS 0 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0
SAMSUNG KS0075 LCD DRIVER & CONTROLLER
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
58. Function Set: RE("1") RS 0 R/W DB7 0 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 1 DB1 0 DB0 0
SAMSUNG KS0075 LCD DRIVER & CONTROLLER
59. Entry Mode Set: BID("1") RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 1 DB0 1
60. Clear Display RS 1 R/W DB7 0 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0
61. Write Data to DDRAM: Write B RS 1 R/W DB7 0 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 0 DB1 0 DB0 1
62. Write Data to DDRAM: Write I RS 1 R/W DB7 0 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 1 DB1 0 DB0 0
63. Write Data for DDRAM: Write D RS 0 R/W DB7 0 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
FRAME FREQUENCY
1/17 DUTY CYCLE
1-line selection period 1 VDD V1 COM1 V4 V5 1 Frame 1 Frame .. 2 3 4 ... 16 17 1 2 3 ... 16 17
Item 1-line selection period Frame frequency
fosc = 270kHz (1 clock = 3.7s)
Display Font Width 5-Dot Font Width 200 clocks 79.4Hz 6-Dot Font Width 240 clocks 66.2Hz
1/33 DUTY CYCLE
1-line selection period 1 VDD V1 COM1 V4 V5 1 Frame 1 Frame .. 2 3 4 ... 32 33 1 2 3 ... 32 33
Item 1-line selection period Frame frequency
fosc = 270kHz (1 clock = 3.7s)
Display Font Width 5-Dot Font Width 100 clocks 81.8Hz 6-Dot Font Width 120 clocks 68.2Hz
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
POWER SUPPLY FOR DRIVING LCD PANEL
WHEN AN EXTERNAL POWER SUPPLY IS USED
VDD
R R R0 R R
VDD V1 V2 V3 V4 V5
VEE
WHEN AN INTERNAL BOOSTER IS USED
Boosting Twice VDD + 1F + VCI GND C1 C2 V5OUT2 V5OUT3 1F + VDD V1 V2 V3 V4 V5 R R R0 R R VDD + 1F + VCI GND C1 C2 V5OUT2 V5OUT3 VDD V1 V2 V3 V4 V5 R R R0 R R Boosting Three Times
1F + 1F +
Can be detached if not using power down mode
Can be detached if not using power down mode
*
Boosted output voltage should not exceed the maximum value (13 V) of the LCD driving voltage. Especially, a voltage of over 4.3V should not be input to the reference voltage (Vci) when boosting three times. A voltage of over 5.5V should not be input to the reference voltage (Vci) when boosting twice. The value of resistance, according to the number of lines, duty ratio and the bias, is shown below. (refer to Table 13)
* *
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
Table 13. Duty Ratio and Power Supply for LCD Driving Item Number of lines Duty ratio Bias Divided resistance R R0 1 1/17 1/5 R R Data 2 or 4 1/33 1/6.7 R 2.7R
MAXIMUM ABSOLUTE RATE
Characteristic Power supply voltage (1) Power supply voltage (2) Input voltage Operating temperature Storage temperature Symbol VDD VLCD VIN TOPR TSTG Value -0.3 to +7.0 VDD -15.0 to VDD +0.3 -0.3 to VDD +0.3 -30 to +85 -55 to +125 Unit V V V C C
Voltage greater than above may damage to the circuit (VDD V1 V2 V3 V4 V5)
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (VDD = 2.7V to 5.5V, Ta = -30 to + 85C) Characteristic Operating voltage Supply current Symbol VDD IDD VIH1 Input voltage (1) (Except OSC1) VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL1 VdCOM VdSEG ILKG IIL f OSC f EC External clock duty tr, tf Voltage converter out2 (Vci = 4.5V) Voltage converter out3 (Vci = 2.7V) Voltage converter input LCD driving voltage VOUT2 VOUT3 Vci VLCD VDD-V5 Ta = 25C, C = 1F, IOUT = 0.25mA, f OSC = 270kHz 1/5 bias 1/6.7 bias -4.3 1.0 3.0 3.0 -5.1 4.5 13.0 13.0 V Condition Internal oscillation or external clock. (VDD = 3.0V, fosc = 270kHz) VDD = 2.7 - 3.0 VDD = 3.0 - 5.5 IOH = -0.1mA IOL = 0.1mA IO = -40A IO = 40A IO = 0.1mA VIN = 0V - VDD VIN = 0V, VDD = 3V (pull up) Rf = 91k 2% (VDD = 5V) Min 2.7 0.7VDD -0.3 -0.3 0.7VDD 0.75VDD 0.8VDD -1 -10 190 125 45 -3.0 Typ 0.15 -50 270 270 50 -4.2 Max 5.5 0.3 VDD 0.2VDD 0.6 VDD 0.2VDD 0.2VDD 0.2VDD 1 V 1 1 -120 350 410 55 0.2 V A kHz kHz % s V V V Unit V mA
Input voltage (2) (Osc1) Output voltage (1) (DB0 - DB7) Output voltage (2) (Except DB0 - DB7) Voltage drop Input leakage current Low input current Internal clock (external Rf)
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
S6A0075
AC CHARACTERISTICS (VDD = 4.5 to 5.5V, Ta = -30 to +85C) Table 14. AC Characteristics Mode E cycle time E rise/fall time (1) Write mode (refer to Figure15) E pulse width (high, low) R/W and RS setup time R/W and RS hold time Data setup time Data hold time E cycle time E rise/fall time E pulse width (high, low) (2) Read mode (refer to Figure 16) R/W and RS setup time R/W and RS hold time Data output delay time Data hold time Serial clock cycle time Serial clock rise/fall time Serial clock width (high, low) (3) Serial interface mode (refer to Figure 17) Chip select setup time Chip select hold time Serial input data setup time Serial input data hold time Serial output data delay time Serial output data hold time Item Symbol tc tr, tf tw tsu1 th1 tsu2 th2 tc tr, tf tw tsu th tD tDH tc tr, tf tw tsu1 th1 tsu2 th2 tD tDH Min 500 230 40 10 60 10 500 230 40 10 5 0.5 200 60 20 100 100 5 Typ Max 20 20 160 20 50 160 ns s ns ns Unit
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
TABLE 14. AC CHARACTERISTICS (VDD = 4.5 to 5.5V, Ta = -30 to +85C) Mode E cycle time E rise / fall time (4) Write mode (refer to Fig-15) E pulse width (high, low) R/W and RS setup time R/W and RS hold time Data setup time Data hold time E cycle time E rise/fall time E pulse width (high, low) (5) Read mode (refer to Figure 16) R/W and RS setup time R/W and RS hold time Data output delay time Data hold time Serial clock cycle time Serial clock rise/fall time Serial clock width (high, low) (6) Serial interface mode (refer to Figure 17) Chip select setup time Chip select hold time Serial input data setup time Serial input data hold time Serial output data delay time Serial output data hold time Item Symbol tc, tr, tf tw tsu1 th1 tsu2 th2 tc tr, tf tw tsu th tD tDH tc tr, tf tw tsu1 th1 tsu2 th2 tD tDH Min 1000 450 60 20 195 10 1000 450 60 20 5 1 400 60 20 200 200 5 Typ Max 25 25 360 20 50 360 ns s ns ns Unit
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
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RS
VIH1 VIL1 tsu1 VIL1 tw
th1 VIL1 th1 tf VIH1 VIL1 tsu2 Valid Data tc
R/W
E tr DB0 - DB7
VIH1 VIL1 VIH1 VIL1
VIL1 th2 VIH1 VIL1
Figure 15. Write Mode
RS
VIH1 VIL1 tsu VIH1 tw
th VIH1 th tf VIH1 VIL1 tD VOH1 VOL1 tDH Valid Data tc VOH1 VOL1
R/W
E tr DB0 - DB7
VIH1 VIL1
VIL1
Figure 16. Read Mode
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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD
tC CS VIL1 tsu1 VIH1 VIL1 tsu2 SID tD SOD VOH1 VOL1 tDH tr tw tf VIH1 VIH1 VIL1 VIL1 th2 VIH1 VIL1 tw VIL1 th1
SCLK
Figure 17. Serial Interface Mode
RESET TIMING (VDD = 2.7 to 5.5V, Ta = -30 to +85 C) Item Reset low level width (refer to Figure 18) Symbol tRES Min 10 Typ Max Unit ms
tRES RESET VIL1 VIL1
Figure 18. Reset Timing Diagram
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